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JK Flip Flop JK触发器
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Tags: Puzzle
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430.523 KB
8 Feb, 2024 @ 10:25am
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斌斌无敌
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JK Flip Flop JK触发器

Description
Design a JK Flip Flop using Logic gates, VCA and signal delay.

src1 represent input J, src2 represent input K, out1 represent output Q.

使用逻辑门，VCA，信号延迟器制作JK触发器。src1为J输入，src2为K输入，out1为Q输出。

J,K,Q的关系为：
J K Qnext
0 0 Qprev
0 100 0
100 0 100
100 100 Qprev`