Steam Community :: Guide :: Default Instruction Set Architectures for Turing Complete

Store Page

Turing Complete

All Discussions Screenshots Artwork Broadcasts Videos News Guides Reviews

Turing Complete > Guides > alexanderpas's Guides

61 ratings

Default Instruction Set Architectures for Turing Complete

By alexanderpas

An overview of the canonical Instruction Set Architectures appearing in the game.

Award

Created by

alexanderpas
Online

Category: Story or Lore

Languages: English

Posted

Updated

29 Apr, 2022 @ 5:30pm

13 Dec, 2022 @ 6:04pm

4,372	Unique Visitors
73	Current Favorites

Guide Index

Overview

OVERTURE

Immidiate 🔴🔴🟤🟤🟤🟤🟤🟤

Calculate 🔴🟢🟤🟤🟤🟤🟤🟤

Copy 🟢🔴🟤🟤🟤🟤🟤🟤

Condition 🟢🟢🟤🟤🟤🟤🟤🟤

LEG

Byte 1: OPCODE

Byte 2: Argument 1

Byte 3: Argument 2

Byte 4: Destination

Registers

Comments

OVERTURE

OVERTURE is the initial ISA, which has 1 byte-wide instructions.

This contains 6 registers, of which the first 4 have designated uses.

Additionally, it contains a single input and a single output, which together are mapped as if they were a 7th register.

The instructions can be split into 4 categories, which can be distinguished by the most significant two bits.

🔴🔴🟤🟤🟤🟤🟤🟤 Immidiate instructions.
🔴🟢🟤🟤🟤🟤🟤🟤 Calculate instructions.
🟢🔴🟤🟤🟤🟤🟤🟤 Copy instructions.
🟢🟢🟤🟤🟤🟤🟤🟤 Condition instructions.

Immidiate 🔴🔴🟤🟤🟤🟤🟤🟤

These instructions represent a number between 0 and 63 (inclusive), which will be put into register 0

Assembly Mnemonics

Generally, these instructions are represented directly by using the value (a number between 0 and 63) directly, since they represent the actual number.

Calculate 🔴🟢🟤🟤🟤🟤🟤🟤

This set of instructions use the 3 least significant bits to indicate which instruction to preform on the contents of Register 1 and Register 2

🔴🟢🟤🟤🟤🔴🔴🔴 OR
🔴🟢🟤🟤🟤🔴🔴🟢 NAND
🔴🟢🟤🟤🟤🔴🟢🔴 NOR
🔴🟢🟤🟤🟤🔴🟢🟢 AND
🔴🟢🟤🟤🟤🟢🔴🔴 ADD
🔴🟢🟤🟤🟤🟢🔴🟢 SUB

OR 🔴🟢🟤🟤🟤🔴🔴🔴

A bitwise OR of the values stored in Register 1 and register 2, with the result being placed in Register 3

NAND 🔴🟢🟤🟤🟤🔴🔴🟢

A bitwise NAND of the values stored in Register 1 and register 2, with the result being placed in Register 3

NOR 🔴🟢🟤🟤🟤🔴🟢🔴

A bitwise NOR of the values stored in Register 1 and register 2, with the result being placed in Register 3

AND 🔴🟢🟤🟤🟤🔴🟢🟢

A bitwise AND of the values stored in Register 1 and register 2, with the result being placed in Register 3

ADD 🔴🟢🟤🟤🟤🟢🔴🔴

Mathematically adds the the values stored in Register 1 and register 2 together, (without support for a carry), with the result being placed in Register 3

SUB 🔴🟢🟤🟤🟤🟢🔴🟢

Subtracts the the values stored in Register 2 from the value stored in register 1 using 2-complements logic, with the result being placed in Register 3

Assembly Mnemonics

The assembly mnemonics for these commands are simply these commands written on their own.

or
nand
nor
and
add
sub

const or 64 const nand 65 const nor 66 const and 67 const add 68 const sub 69

Copy 🟢🔴🟤🟤🟤🟤🟤🟤

These instructions allow you to represent a copy action between a source location and a destination location.

There are 7 possible sources to read from:

🟢🔴🔴🔴🔴🟤🟤🟤 Register 0
🟢🔴🔴🔴🟢🟤🟤🟤 Register 1
🟢🔴🔴🟢🔴🟤🟤🟤 Register 2
🟢🔴🔴🟢🟢🟤🟤🟤 Register 3
🟢🔴🟢🔴🔴🟤🟤🟤 Register 4
🟢🔴🟢🔴🟢🟤🟤🟤 Register 5
🟢🔴🟢🟢🔴🟤🟤🟤 Input

There are 7 possible destinations to write to:

🟢🔴🟤🟤🟤🔴🔴🔴 Register 0
🟢🔴🟤🟤🟤🔴🔴🟢 Register 1
🟢🔴🟤🟤🟤🔴🟢🔴 Register 2
🟢🔴🟤🟤🟤🔴🟢🟢 Register 3
🟢🔴🟤🟤🟤🟢🔴🔴 Register 4
🟢🔴🟤🟤🟤🟢🔴🟢 Register 5
🟢🔴🟤🟤🟤🟢🟢🔴 Output

Assembly Mnemonics

A common method of representing the commands is by idividually specifying the parts of the command and adding them together using the OR operator.

const cp 128

const s0 0 const s1 8 const s2 16 const s3 24 const s4 32 const s5 40 const in 48

const d0 0 const d1 1 const d2 2 const d3 3 const d4 4 const d5 5 const out 6

Example, which allows you to copy from Register 3 to Register 0

cp|s3|d0

Off Label Usage

This section is non-normative

Most common implementations are implemented in such way that if you specify the non-defined option as a source, a zero is read

🟢🔴🟢🟢🟢🟤🟤🟤 Clear Destination Register

Condition 🟢🟢🟤🟤🟤🟤🟤🟤

This set of instructions allow you to jump to a certain point in your program.

The destination of the jump is specified by the Register 0.

The jump will only be performed if the value in Register 3 matches the condition set by the least significant 3 bits of the instruction.

🟢🟢🟤🟤🟤🔴🔴🔴 Never
🟢🟢🟤🟤🟤🔴🔴🟢 Equals 0
🟢🟢🟤🟤🟤🔴🟢🔴 Less Than 0
🟢🟢🟤🟤🟤🔴🟢🟢 Less than or equals 0
🟢🟢🟤🟤🟤🟢🔴🔴 Always
🟢🟢🟤🟤🟤🟢🔴🟢 Not equals 0
🟢🟢🟤🟤🟤🟢🟢🔴 Greater than or equals 0
🟢🟢🟤🟤🟤🟢🟢🟢 Greater than 0

Assembly Mnemonics

const never 192 const eq 193 const less 194 const less_eq 195 const always 196 const not_eq 197 const greater_eq 198 const greater 199

LEG

The LEG architecture uses 4-byte wide instructions, and has 6 registers, with the counter also being acesible as the 7th register, and the input/output as the 8th register

Byte 1: OPCODE

Arithmic Opcodes

This set of instructions use the 3 least significant bits to indicate which instruction to preform on the contents of Register 1 and Register 2

🟤🟤🔴🔴🔴🔴🔴🔴 ADD
🟤🟤🔴🔴🔴🔴🔴🟢 SUB
🟤🟤🔴🔴🔴🔴🟢🔴 AND
🟤🟤🔴🔴🔴🔴🟢🟢 OR
🟤🟤🔴🔴🔴🟢🔴🔴 NOT
🟤🟤🔴🔴🔴🟢🔴🟢 XOR

ADD 🟤🟤🔴🔴🔴🔴🔴🔴

Mathematically adds the the values provided by Argument 1 and Argument 2 together, (without support for a carry), with the result being stored at the location provided by the destination.

SUB 🟤🟤🔴🔴🔴🔴🔴🟢

Subtracts the the value provided by Argument 2 from the value provided by Argument 1 using 2-complements logic, with the result being stored at the location provided by the destination.

AND 🟤🟤🔴🔴🔴🔴🟢🔴

A bitwise AND of the values provided by Argument 1 and Argument 2, with the result being stored at the location provided by the destination.

OR 🟤🟤🔴🔴🔴🔴🟢🟢

A bitwise OR of the values provided by Argument 1 and Argument 2, with the result being stored at the location provided by the destination.

NOT 🟤🟤🔴🔴🔴🟢🔴🔴

bitwise inverts the value provided by Argument 1, with the result being stored at the location provided by the destination.

XOR 🟤🟤🔴🔴🔴🟢🔴🟢

A bitwise XOR of the values provided by Argument 1 and Argument 2, with the result being stored at the location provided by the destination.

Jumping Opcodes

This set of instructions use the 3 least significant bits to determine when to change the program counter to the specific value provided by the destination based the value provided by Argument 1 and Argument 2

🟤🟤🟢🔴🔴🔴🔴🔴 IF_EQUAL
🟤🟤🟢🔴🔴🔴🔴🟢 IF_NOT_EQUAL
🟤🟤🟢🔴🔴🔴🟢🔴 IF_LESS
🟤🟤🟢🔴🔴🔴🟢🟢 IF_LESS_OR_EQUAL
🟤🟤🟢🔴🔴🟢🔴🔴 IF_GREATER
🟤🟤🟢🔴🔴🟢🔴🟢 IF_GREATER_OR_EQUAL

IF_EQUAL 🟤🟤🟢🔴🔴🔴🔴🔴

Jumps to the location provided by destination when the value provided by Argument 1 is equal to the value provided by Argument 2

IF_NOT_EQUAL 🟤🟤🟢🔴🔴🔴🔴🟢

Jumps to the location provided by destination when the value provided by Argument 1 is not equal to the value provided by Argument 2

IF_LESS 🟤🟤🟢🔴🔴🔴🟢🔴

Jumps to the location provided by destination when the value provided by Argument 1 is less than the value provided by Argument 2

IF_LESS_OR_EQUAL 🟤🟤🟢🔴🔴🔴🟢🟢

Jumps to the location provided by destination when the value provided by Argument 1 is not greater than the value provided by Argument 2

IF_GREATER 🟤🟤🟢🔴🔴🟢🔴🔴

Jumps to the location provided by destination when the value provided by Argument 1 is greater than the value provided by Argument 2

IF_GREATER_OR_EQUAL 🟤🟤🟢🔴🔴🟢🔴🟢

Jumps to the location provided by destination when the value provided by Argument 1 is not less than the value provided by Argument 2

Argument Modification

You can change the behavior of Argument 1 and Argument 2 based on the state of the 2 most significant bits of the opcode

🔴🔴🟤🟤🟤🟤🟤🟤 Default (No modification)
🟢🟤🟤🟤🟤🟤🟤🟤 Argument 1
🟤🟢🟤🟤🟤🟤🟤🟤 Argument 2

Default (No modification) 🔴🔴🟤🟤🟤🟤🟤🟤

By default, Both Argument 1 and Argument 2 represent a location where the data can be found as specified in the register section below.

Argument 1 🟢🟤🟤🟤🟤🟤🟤🟤

If the 8th bit has been set, Argument 1 instead contains an actual 8-bit value

Argument 2 🟤🟢🟤🟤🟤🟤🟤🟤

If the 7th bit has been set, Argument 2 instead contains an actual 8-bit value

Byte 2: Argument 1

If the 8th bit of the opcode has been set, this represents an actual 8-bit number.

Otherwise, it represents a location where the data can be found as specified in the register section below.

Byte 3: Argument 2

If the 7th bit of the opcode has been set, this represents an actual 8-bit number.

Otherwise, it represents a location where the data can be found as specified in the register section below.

Byte 4: Destination

If an arithmic opcode is used, this represents the location where the result of the calculation will be stored, as specified in the register section below.

If an jumping opcode is used, this represents the value of the counter after executing this command.

Registers

The LEG architecture contains 6 freely usable registers, as well as a controllable counter which can be acessed as if it was the 7th register.

Additionally, it contains a single input and a single output, which together are mapped as if they were a 8th register.

🔴🔴🔴🔴🔴🔴🔴🔴 Register 0
🔴🔴🔴🔴🔴🔴🔴🟢 Register 1
🔴🔴🔴🔴🔴🔴🟢🔴 Register 2
🔴🔴🔴🔴🔴🔴🟢🟢 Register 3
🔴🔴🔴🔴🔴🟢🔴🔴 Register 4
🔴🔴🔴🔴🔴🟢🔴🟢 Register 5
🔴🔴🔴🔴🔴🟢🟢🔴 Counter
🔴🔴🔴🔴🔴🟢🟢🟢 Input / Output

13 Comments

< >

BtB 5 Mar @ 9:54pm

Thanks. The most irritating part of any of the Overture stages was constantly checking the specifications. With two monitors, this is a real time-saver.

maxtch 28 May, 2024 @ 10:35am

@Reyquiem If you are expanding the ISA, it may be better to use some of the unused ALU instruction encoding to be your memory load/store instruction, and remove the I/O register accordingly as you now have memory-mapped I/O. This gives you a classic Harvard architecture RISC load/store machine.

Reyquiem 28 Feb, 2024 @ 8:09pm

I never used the ability for LEG to directly modify the program counter, so in my most recent playthrough I reworked it so the 7th "register" connects to the space in RAM at the address stored in one of the other registers. It works pretty well, though it might have been ultimately more helpful to have a command that allows the RAM address to be specified as an argument. Maybe I'll try that another time.

Frootloopia 17 Nov, 2023 @ 6:39pm

Alternately, you could also add a pass-through into the ALU.

Frootloopia 17 Nov, 2023 @ 6:36pm

@pyro main
You can just ADD a 0 to the value you want to put into the register, it effectively is just the copy function.

DoGGy 15 Feb, 2023 @ 1:25pm

nate_4000, you can add additinal opcode for this action

USPS Worker 9 Feb, 2023 @ 7:17pm

hey, how would i put a specific value to a register in leg?

alexanderpas [author] 21 Jan, 2023 @ 5:41am

Yes, they are the same bits in LEG, but located in different bytes.

If you want to add register 0 and register 0 together and store the result in register 0, the 4 bytes of that command read: `0 0 0 0`

Keyojin 8 Jan, 2023 @ 7:01pm

Good info. But how do you set up the assembly code for the leg? Add and register 0 are the same bits.

M. T. Kalaschnikow 18 Nov, 2022 @ 1:05pm

Thank you so much for this guide!
I got stuck at 'wire spaghetti' because I didn't know exactly what to do. (Which Bit does what etc.)
So I buildt the complete LEG PC blindly without a test following the instructions above and it worked at the first try!
And not only at 'wire spaghetti' but also at ALL following levels of CPU architecture 2!

< >